Data communications devices such as Ethernet network devices typically include a serializer/deserializer (SERDES) device. SERDES devices include a serializer that converts a parallel data stream into serial data stream on a transmit side. The SERDES also include a deserializer that converts a serial data stream into a parallel data stream on a receive side. The serial data stream that is generated by the SERDES includes an embedded clock signal. Circuits associated with the deserializer recover the embedded clock signal.
Referring to FIG. 1, a data communications device 10 includes a SERDES device 12 that receives and sends parallel data with another device 14, such as a medium access control (MAC) device, a physical layer (PHY) device and/or other suitable devices. The SERDES device 12 includes a serializer device 16 and a deserializer device 18. The serializer device 16 receives a parallel data stream from the device 14 and converts the parallel data stream into a serial data stream. The deserializer device 18 receives a serial data stream and converts the serial data stream into a parallel data stream. The deserializer device 18 outputs the parallel data stream to the device 14 for processing.
A clock generator 20 generates a reference clock signal. For example, the clock generator 20 may include an crystal oscillator (XOSC). A phase-locked loop (PLL) device 22 and the serializer 16 receive a reference clock signal 24 from the clock generator 20. The PLL device 22 includes an interpolator device 25, which adjusts the phase of the reference clock signal 24 to match a recovered clock signal in the received serial data stream.
Referring now to FIG. 2, the SERDES device 12 is usually tested following manufacture and/or during use to verify proper operation. For example, the parallel data stream that is recovered by a deserializer device 18 may be required to have a minimum number of errors when a test signal is transmitted to the deserializer device 18. An automatic testing equipment (ATE) system 32 is typically employed to test the SERDES device 12. The ATE system 32 generates the test signal that is output to the serializer 16. The output of the serializer device 16 is looped back to the deserializer device 18 and is compared to the test signal. If the two sufficiently match, the SERDES 12 passes the test. If not, the SERDES 12 fails the test.
The exemplary ATE system 32 includes a data generator 34 that communicates with a data checker 36. The data generator 34 generates the parallel test signal and outputs the parallel test signal to the serializer device 16. The serializer device 16 converts the parallel test signal into a serial data stream. The output of the serializer device 16 is looped back to the input of the deserializer device 18. The deserializer device 18 converts the serial data stream into a recovered parallel data stream.
The data checker 36 receives the recovered parallel data stream and compares the recovered parallel data stream with the parallel test data signal from the data generator 34 to verify proper operation of the SERDES device 12. The data generator 34 and the data checker 36 may also be included in a built-in self-test module in the SERDES device 12, which may be utilized to test the SERDES device 12.
Referring now to FIG. 3, the interpolator device 25 communicates with the deserializer device 18 and includes a phase select module 50, a phase shift module 52 and a phase selector 54. The phase shift module 52 receives the reference clock signal 24 and generates M clock signals that are offset in phase by 360/M degrees. One of the M clock signals is selected as a recovered clock signal 55. The phase select module 50 receives the recovered clock signal 55 and the reference clock signal 24 and generates a select signal 56, which selects one of the M clock signals. The M clock signals that are output by the phase shift module 52 are input to the phase selector 54, which receives the select signal 56 from said phase select module 50.
The phase select module 50 detects when signal drift occurs and adjusts the select signal 56 to advance or delay a phase of the recovered clock signal 55. The select signal 56 selects a specific phase-shifted copy of the reference clock signal 24 that is output by the selector 54 so that the reference clock signal 24 and the recovered clock signal 55 are synchronized.
The ATE system 32 tests the SERDES device 12 under simulated conditions. However, one important function of the deserializer device 18 is clock recovery. During normal operations, the deserializer device 18 synchronizes the recovered clock signal in the serial data stream with the reference clock signal. Since the output of the serializer device 16 is looped back to the deserializer device 18, the interpolator device 25 is not tested sufficiently. In other words, the serializer device 16 is frequency-locked with the deserializer device 18. If there is a manufacturing defect in the interpolator device 25 or in the phase shift module 52 that generate copies of the reference clock signal, the testing by the ATE system 32 will not detect these errors.